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authorYann Herklotz <git@yannherklotz.com>2020-04-15 17:28:21 +0100
committerYann Herklotz <git@yannherklotz.com>2020-04-15 17:28:21 +0100
commit18a888d24e5bfcc75122a682b690ec4788584dd2 (patch)
treea9dc9b7d5c5245daae4d16f33c739819618a057a /src/verilog/Verilog.v
parent4edb752a9dc80e92173b52dccd3708306a1913b0 (diff)
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Create Value module for bitvectors
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