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| author | Nadesh Ramanathan <nadeshramanathan88@gmail.com> | 2020-07-07 15:33:25 +0100 |
|---|---|---|
| committer | Nadesh Ramanathan <nadeshramanathan88@gmail.com> | 2020-07-07 15:33:25 +0100 |
| commit | 65ac86da554770ba0e3a24d187037c6a72a8725b (patch) | |
| tree | 6d1e0085f17f7e565733ac821ec70c3cd0d81dde /src/verilog | |
| parent | b141f1e5b58aaabd091f30d2371e43712fbaef38 (diff) | |
| download | vericert-kvx-65ac86da554770ba0e3a24d187037c6a72a8725b.tar.gz vericert-kvx-65ac86da554770ba0e3a24d187037c6a72a8725b.zip | |
added counter in testbench
Diffstat (limited to 'src/verilog')
| -rw-r--r-- | src/verilog/PrintVerilog.ml | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 5265c97..f8d597a 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -169,9 +169,12 @@ let testbench = "module testbench; always #5 clk = ~clk; + reg [31:0] count; + initial count = 0; always @(posedge clk) begin + count <= count + 1; if (finish == 1) begin - $display(\"finished: %d\", return_val); + $display(\"finished: %d cycles %d\", return_val, count); $finish; end end |