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| author | Yann Herklotz <git@yannherklotz.com> | 2020-07-05 02:46:11 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2020-07-05 02:46:11 +0100 |
| commit | d6c6c87d61dc10b1acaeb056975675c7e523f1ef (patch) | |
| tree | 9b21d35d5de8606a231c83a1de75c0586410642a /src/verilog | |
| parent | 322f3a1c2d547490b0e92a8f1ef937e1d68c2a6b (diff) | |
| download | vericert-kvx-d6c6c87d61dc10b1acaeb056975675c7e523f1ef.tar.gz vericert-kvx-d6c6c87d61dc10b1acaeb056975675c7e523f1ef.zip | |
Remove admitted in mis_stepp_Vdecl
Diffstat (limited to 'src/verilog')
| -rw-r--r-- | src/verilog/Verilog.v | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index 1513330..064474a 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -610,8 +610,8 @@ Inductive mi_stepp : fext -> reg_associations -> arr_associations -> stmnt_runp f sr0 sa0 st sr1 sa1 -> mi_stepp f sr0 sa0 (Valways_comb c st) sr1 sa1 | mi_stepp_Vdecl : - forall f sr sa lhs rhs io, - mi_stepp f sr sa (Vdeclaration (Vdecl io lhs rhs)) sr sa. + forall f sr sa d, + mi_stepp f sr sa (Vdeclaration d) sr sa. Hint Constructors mi_stepp : verilog. Inductive mis_stepp : fext -> reg_associations -> arr_associations -> @@ -743,8 +743,7 @@ Inductive step : genv -> state -> Events.trace -> state -> Prop := forall g m asr i r sf pc mst asa, mst = mod_st m -> step g (Returnstate (Stackframe r m pc asr asa :: sf) i) Events.E0 - (State sf m pc ((asr # mst <- (posToValue pc)) # r <- i) - asa). + (State sf m pc ((asr # mst <- (posToValue pc)) # r <- i) asa). Hint Constructors step : verilog. Inductive initial_state (p: program): state -> Prop := |