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Diffstat (limited to 'src/Verilog/VerilogAST.v')
| -rw-r--r-- | src/Verilog/VerilogAST.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/Verilog/VerilogAST.v b/src/Verilog/VerilogAST.v index 362fe45..5886652 100644 --- a/src/Verilog/VerilogAST.v +++ b/src/Verilog/VerilogAST.v @@ -32,6 +32,9 @@ Inductive value : Type := | VBool (b : bool) | VArray (l : list value). +Inductive literal : Type := +| LitArray (l : list bool). + Definition cons_value (a b : value) : value := match a, b with | VBool _, VArray b' => VArray (a :: b') |