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-rw-r--r--src/hls/HTLPargen.v14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/hls/HTLPargen.v b/src/hls/HTLPargen.v
index 9746f92..06b3fcb 100644
--- a/src/hls/HTLPargen.v
+++ b/src/hls/HTLPargen.v
@@ -33,11 +33,11 @@ Require Import vericert.hls.RTLPar.
Require Import vericert.hls.ValueInt.
Require Import vericert.hls.Verilog.
-Hint Resolve AssocMap.gempty : htlh.
-Hint Resolve AssocMap.gso : htlh.
-Hint Resolve AssocMap.gss : htlh.
-Hint Resolve Ple_refl : htlh.
-Hint Resolve Ple_succ : htlh.
+#[local] Hint Resolve AssocMap.gempty : htlh.
+#[local] Hint Resolve AssocMap.gso : htlh.
+#[local] Hint Resolve AssocMap.gss : htlh.
+#[local] Hint Resolve Ple_refl : htlh.
+#[local] Hint Resolve Ple_succ : htlh.
Definition assignment : Type := expr -> expr -> stmnt.
@@ -74,10 +74,10 @@ Module HTLState <: State.
s1.(st_controllogic)!n = None
\/ s2.(st_controllogic)!n = s1.(st_controllogic)!n) ->
st_incr s1 s2.
- Hint Constructors st_incr : htlh.
+ #[local] Hint Constructors st_incr : htlh.
Definition st_prop := st_incr.
- Hint Unfold st_prop : htlh.
+ #[local] Hint Unfold st_prop : htlh.
Lemma st_refl : forall s, st_prop s s.
Proof. auto with htlh. Qed.