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-rw-r--r--src/hls/PrintVerilog.ml2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml
index a2700a1..a5fa554 100644
--- a/src/hls/PrintVerilog.ml
+++ b/src/hls/PrintVerilog.ml
@@ -75,7 +75,7 @@ let pprint_binop l r =
let unop = function
| Vneg -> " - "
- | Vnot -> " ! "
+ | Vnot -> " ~ "
let register a =
match PMap.find_opt a !name_map with