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Diffstat (limited to 'src/verilog/PrintVerilog.mli')
| -rw-r--r-- | src/verilog/PrintVerilog.mli | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli deleted file mode 100644 index 6a15ee9..0000000 --- a/src/verilog/PrintVerilog.mli +++ /dev/null @@ -1,25 +0,0 @@ -(* - * Vericert: Verified high-level synthesis. - * Copyright (C) 2019-2020 Yann Herklotz <yann@yannherklotz.com> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <https://www.gnu.org/licenses/>. - *) - -val pprint_stmnt : int -> Verilog.stmnt -> string - -val print_value : out_channel -> ValueInt.value -> unit - -val print_program : bool -> out_channel -> Verilog.program -> unit - -val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit |