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* Add todo for missing logic around instantiationsmichalisMichalis Pardalos2020-11-231-0/+1
* Add wires and use them for output of instancesMichalis Pardalos2020-11-235-23/+55
* Separate HTL instantiations from Verilog onesMichalis Pardalos2020-11-237-21/+30
* Print HTL args as reg_{n}, not x{n}Michalis Pardalos2020-11-231-7/+7
* Translate instantiations from HTL to verilogMichalis Pardalos2020-11-233-2/+7
* Print instantiations in HTL outputMichalis Pardalos2020-11-233-14/+29
* Add a field in HTL modules for instancesMichalis Pardalos2020-11-235-37/+102
* Print all modules in verilog outputMichalis Pardalos2020-11-231-13/+11
* Generate (invalid) module instantiations for callsMichalis Pardalos2020-11-235-21/+33
* fixing adimpardalos-michalisNadesh Ramanathan2020-11-193-21/+18
* scriptsNadesh Ramanathan2020-11-192-1/+7
* poly numbers and R scripts for basic statsNadesh Ramanathan2020-11-182-0/+49
* removing optimisation flagNadesh Ramanathan2020-11-171-1/+1
* updated luNadesh Ramanathan2020-11-171-20/+18
* missing libraryNadesh Ramanathan2020-11-171-0/+3
* Merge branch 'dev-experiments'Yann Herklotz2020-11-1727-96/+203
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| * final checks reworked and including compilation time in scriptdev-experimentsNadesh Ramanathan2020-11-1725-32/+168
| * lu fixNadesh Ramanathan2020-11-151-1/+1
| * some fixesNadesh Ramanathan2020-11-155-22/+36
* | More fixes to the proofYann Herklotz2020-11-141-4/+5
* | [Fix #9] Fix correctness proof for OshrximmYann Herklotz2020-11-141-4/+90
* | Update MakefileYann Herklotz2020-11-141-1/+1
* | Add more tracking files to github workflowYann Herklotz2020-11-141-0/+6
* | Add manual trigger for workflowsYann Herklotz2020-11-141-1/+1
* | Add manual trigger for workflowsYann Herklotz2020-11-141-0/+1
* | Update lu.c and update Makefile with extractionYann Herklotz2020-11-142-40/+35
* | Merge branch 'dev-experiments'Yann Herklotz2020-11-1432-328/+611
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| * polybench editsNadesh Ramanathan2020-11-1129-310/+295
| * dividerNadesh Ramanathan2020-11-111-0/+81
| * Adding synthesis scriptsNadesh Ramanathan2020-11-103-0/+110
| * fixing luNadesh Ramanathan2020-11-101-14/+4
| * fixing durbinNadesh Ramanathan2020-11-101-8/+2
| * fixing gemverNadesh Ramanathan2020-11-101-6/+8
| * remove benchmarks from listNadesh Ramanathan2020-11-101-2/+0
| * fixes for choleskyNadesh Ramanathan2020-11-101-26/+22
| * fixes for fwNadesh Ramanathan2020-11-101-1/+4
| * fixing nussinovNadesh Ramanathan2020-11-101-5/+7
| * Merge branch 'dev-experiments' of https://github.com/ymherklotz/vericert into...Nadesh Ramanathan2020-11-102-9/+16
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| | * Fix benchmarks to make them compileYann Herklotz2020-11-102-9/+16
| * | adding flagNadesh Ramanathan2020-11-101-1/+1
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| * error messagingNadesh Ramanathan2020-11-091-6/+6
| * added some checksNadesh Ramanathan2020-11-091-0/+17
| * a script to execute polybench on vericertNadesh Ramanathan2020-11-092-0/+53
| * Fix Makefile for verilog backendYann Herklotz2020-11-094-7/+8
| * Add small changes to durbin and adpcmYann Herklotz2020-11-092-64/+99
| * Fix pretty printing bug in VerilogYann Herklotz2020-11-091-2/+2
| * Fix printing of negative numbersYann Herklotz2020-11-091-1/+5
* | Fix benchmarks to make them compileYann Herklotz2020-11-102-9/+16
* | Fix compilation issueYann Herklotz2020-11-103-12/+12
* | Change and add back HTLgenYann Herklotz2020-11-095-16/+66
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