Commit message (Expand) | Author | Age | Files | Lines | |
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* | Small optimisations to proof | Yann Herklotz | 2020-05-31 | 1 | -5/+4 |
* | Merge branch 'develop' of github.com:ymherklotz/CoqUp into develop | Yann Herklotz | 2020-05-29 | 1 | -6/+3 |
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| * | Improve automation in HTLgenspec. | James Pollard | 2020-05-29 | 1 | -6/+3 |
* | | Fix compilation moving to PTree | Yann Herklotz | 2020-05-29 | 3 | -25/+34 |
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* | Change AssocMap to Maps.PTree | Yann Herklotz | 2020-05-29 | 1 | -3/+5 |
* | Add more proofs and remove Admitted | Yann Herklotz | 2020-05-27 | 1 | -49/+43 |
* | Add top level definition | Yann Herklotz | 2020-05-27 | 2 | -138/+153 |
* | Working on automation | Yann Herklotz | 2020-05-26 | 1 | -62/+48 |
* | Finished proof of spec completely | Yann Herklotz | 2020-05-26 | 2 | -5/+94 |
* | Finished second pass and fixed bug | Yann Herklotz | 2020-05-26 | 2 | -18/+37 |
* | Finished proving the first case | Yann Herklotz | 2020-05-25 | 1 | -1/+6 |
* | Continuing work on proving specification | Yann Herklotz | 2020-05-25 | 2 | -22/+218 |
* | Add HTLgen | Yann Herklotz | 2020-05-24 | 1 | -1/+337 |
* | Finish the proof with most assumptions | Yann Herklotz | 2020-05-21 | 2 | -29/+150 |
* | Add proof of translation correctness | Yann Herklotz | 2020-05-20 | 2 | -17/+200 |
* | Add simulation diagram | Yann Herklotz | 2020-05-08 | 1 | -5/+53 |
* | Add match_states Inductive | Yann Herklotz | 2020-05-07 | 1 | -0/+29 |
* | Remove HTLgen and create the specification | Yann Herklotz | 2020-05-07 | 2 | -163/+92 |
* | Redefine HTL for intermediate Verilog language | Yann Herklotz | 2020-05-07 | 1 | -0/+18 |
* | Add equality check for value | Yann Herklotz | 2020-05-04 | 2 | -2/+2 |
* | Add proofs and specification of Verilog conversion | Yann Herklotz | 2020-05-03 | 2 | -0/+158 |
* | Add state transition conversion functions | Yann Herklotz | 2020-05-03 | 1 | -2/+14 |
* | Add documentation and conform to specification | Yann Herklotz | 2020-04-29 | 1 | -24/+41 |
* | Only generate clocked always blocks | Yann Herklotz | 2020-04-17 | 1 | -13/+13 |
* | Make proofs simpler using auto | Yann Herklotz | 2020-04-15 | 1 | -59/+45 |
* | Add proof about state wf | Yann Herklotz | 2020-04-08 | 1 | -40/+193 |
* | Add partial proof of well formed state | Yann Herklotz | 2020-04-06 | 1 | -24/+136 |
* | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 1 | -100/+128 |
* | Complete translation from simple RTL to Verilog | Yann Herklotz | 2020-04-01 | 1 | -101/+162 |
* | Convert from RTL to Verilog directly | Yann Herklotz | 2020-03-31 | 1 | -18/+20 |
* | Add more operators and print them | Yann Herklotz | 2020-03-31 | 1 | -37/+69 |
* | Improve Verilog error messages | Yann Herklotz | 2020-03-31 | 1 | -1/+7 |
* | Rename to transf_program | Yann Herklotz | 2020-03-29 | 1 | -1/+1 |
* | Complete conversion from HTL to Verilog | Yann Herklotz | 2020-03-29 | 1 | -8/+91 |
* | Add Verilog generation from HTL | Yann Herklotz | 2020-03-29 | 1 | -0/+135 |
* | Remove unnecessary examples from HTL | Yann Herklotz | 2020-03-29 | 1 | -6/+1 |
* | Create HTLgen | Yann Herklotz | 2020-03-25 | 3 | -148/+5 |
* | Add Maps and HTL.v | Yann Herklotz | 2020-03-25 | 1 | -0/+186 |
* | Create a new direct translation | Yann Herklotz | 2020-03-22 | 2 | -14/+125 |
* | Update names of directories | Yann Herklotz | 2020-03-19 | 1 | -0/+37 |