| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Refine the semantics | Yann Herklotz | 2020-05-04 | 1 | -42/+63 |
| * | Change to State | Yann Herklotz | 2020-05-03 | 1 | -21/+22 |
| * | Add CompCert semantics for Verilog | Yann Herklotz | 2020-04-24 | 1 | -81/+152 |
| * | Add stmnt_runp inductive | Yann Herklotz | 2020-04-22 | 1 | -27/+106 |
| * | Use State in semantics instead of splitting it up | Yann Herklotz | 2020-04-22 | 1 | -95/+98 |
| * | Fix Verilog.v | Yann Herklotz | 2020-04-17 | 1 | -1/+1 |
| * | Add main module run | Yann Herklotz | 2020-04-17 | 1 | -50/+78 |
| * | Add Verilog semantics with new Verilog module | Yann Herklotz | 2020-04-15 | 1 | -33/+326 |
| * | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 1 | -7/+8 |
| * | Update compilation | Yann Herklotz | 2020-04-01 | 1 | -5/+36 |
| * | Add documentation and fix makefile for Compcert | Yann Herklotz | 2020-03-31 | 1 | -1/+1 |
| * | Add more operators and print them | Yann Herklotz | 2020-03-31 | 1 | -3/+10 |
| * | Improve Verilog error messages | Yann Herklotz | 2020-03-31 | 1 | -1/+4 |
| * | Change Verilog AST back to more traditional AST | Yann Herklotz | 2020-03-29 | 1 | -30/+44 |
| * | Update AST and value representations | Yann Herklotz | 2020-03-29 | 1 | -213/+42 |
| * | Rename Verilog AST files | Yann Herklotz | 2020-03-29 | 1 | -0/+253 |
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index : vericert-kvx | |
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