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* Add lessdef for valuesYann Herklotz2020-05-081-3/+10
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* Add AssocMapYann Herklotz2020-05-084-47/+93
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* Redefine HTL for intermediate Verilog languageYann Herklotz2020-05-071-76/+69
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* Use associations instead of stateYann Herklotz2020-05-072-70/+69
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* Rename assoclist to assocsetYann Herklotz2020-05-072-28/+28
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* Add changes to valueYann Herklotz2020-05-061-2/+9
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* Refine test fileYann Herklotz2020-05-051-5/+2
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* Minimised manual simulationYann Herklotz2020-05-052-45/+14
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* Simplifications to proofYann Herklotz2020-05-053-18/+15
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* Finish manual simulationYann Herklotz2020-05-052-5/+68
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* Add equality check for valueYann Herklotz2020-05-042-16/+22
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* Refine the semanticsYann Herklotz2020-05-043-56/+130
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* Add code to debug execution of HLSsave/old-stepYann Herklotz2020-05-031-0/+73
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* Add hex notation to valuesYann Herklotz2020-05-031-0/+9
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* Change to StateYann Herklotz2020-05-031-21/+22
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* Add CompCert semantics for VerilogYann Herklotz2020-04-241-81/+152
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* Add valueToInt functionYann Herklotz2020-04-241-0/+3
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* Add stmnt_runp inductiveYann Herklotz2020-04-221-27/+106
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* Remove unnecessary LemmaYann Herklotz2020-04-221-8/+1
| | | | | Still cannot run these functions inside Coq itself, however, they work when they are extracted to Caml.
* Use State in semantics instead of splitting it upYann Herklotz2020-04-221-95/+98
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* Improve printing of resultsYann Herklotz2020-04-222-7/+13
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* Fix Verilog.vYann Herklotz2020-04-171-1/+1
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* Add main module runYann Herklotz2020-04-172-51/+79
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* Fix printing with new Verilog ASTYann Herklotz2020-04-172-26/+54
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* Add Verilog semantics with new Verilog moduleYann Herklotz2020-04-151-33/+326
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* Create Value module for bitvectorsYann Herklotz2020-04-151-0/+217
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* Handle loops and conditionals correctlyYann Herklotz2020-04-022-12/+53
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* Update compilationYann Herklotz2020-04-013-14/+81
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* Add documentation and fix makefile for CompcertYann Herklotz2020-03-312-1/+26
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* Add more operators and print themYann Herklotz2020-03-312-4/+15
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* Improve Verilog error messagesYann Herklotz2020-03-311-1/+4
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* Fix Verilog printingYann Herklotz2020-03-312-33/+35
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* Change Verilog AST back to more traditional ASTYann Herklotz2020-03-291-30/+44
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* Remove unnecessary examples from HTLYann Herklotz2020-03-291-4/+4
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* Update AST and value representationsYann Herklotz2020-03-291-213/+42
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* Rename Verilog AST filesYann Herklotz2020-03-293-0/+0
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* Update printingYann Herklotz2020-03-253-38/+52
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* Remove dunes and make the build recursiveYann Herklotz2020-03-251-4/+0
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* Rename to HTLYann Herklotz2020-03-231-18/+28
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* Create intermediate VTL languageYann Herklotz2020-03-221-0/+63
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* Add compcert library to coquplibYann Herklotz2020-03-221-8/+9
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* Lower case foldersYann Herklotz2020-03-194-0/+341
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