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* Update Verilog AST with flat arrayYann Herklotz2020-02-182-0/+7
* Create translationYann Herklotz2020-02-181-0/+18
* Update license to be compatible with CompCertYann Herklotz2020-02-179-16/+173
* Add pretty printing for Verilog integrated with CompCertYann Herklotz2020-02-1716-238/+313
* Add project files and compcert interconnectYann Herklotz2020-02-141-0/+79
* Improve the Coq sources and add extractionYann Herklotz2020-02-133-45/+28
* Add show typeclassYann Herklotz2020-02-041-0/+42
* Add nix fileYann Herklotz2020-02-041-2/+13
* Short proof and add TacticsYann Herklotz2020-01-292-12/+31
* Proof of nat_to_value_is_flat addedYann Herklotz2020-01-291-29/+28
* Trying some more proofsYann Herklotz2020-01-241-7/+50
* Added value_to_natYann Herklotz2020-01-242-15/+28
* Reorder to let it compile againYann Herklotz2020-01-241-37/+35
* Finish some proofs and convert to natYann Herklotz2020-01-241-12/+16
* Add some proofs about valuesYann Herklotz2020-01-231-94/+181
* Move into src directoryYann Herklotz2020-01-223-0/+119