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* Add simulation diagramYann Herklotz2020-05-081-5/+53
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* Add lessdef for valuesYann Herklotz2020-05-081-3/+10
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* Add AssocMapYann Herklotz2020-05-084-47/+93
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* Add match_states InductiveYann Herklotz2020-05-071-0/+29
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* Remove HTLgen and create the specificationYann Herklotz2020-05-072-163/+92
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* Redefine HTL for intermediate Verilog languageYann Herklotz2020-05-072-76/+87
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* Use associations instead of stateYann Herklotz2020-05-072-70/+69
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* Rename assoclist to assocsetYann Herklotz2020-05-072-28/+28
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* Remove Admitted Maps LemmaYann Herklotz2020-05-071-6/+0
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* Add changes to valueYann Herklotz2020-05-061-2/+9
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* Refine test fileYann Herklotz2020-05-051-5/+2
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* Minimised manual simulationYann Herklotz2020-05-052-45/+14
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* Simplifications to proofYann Herklotz2020-05-053-18/+15
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* Finish manual simulationYann Herklotz2020-05-052-5/+68
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* Add equality check for valueYann Herklotz2020-05-047-21/+27
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* Refine the semanticsYann Herklotz2020-05-043-56/+130
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* Add code to debug execution of HLSsave/old-stepYann Herklotz2020-05-031-0/+73
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* Add proofs and specification of Verilog conversionYann Herklotz2020-05-032-0/+158
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* Add state transition conversion functionsYann Herklotz2020-05-031-2/+14
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* Add hex notation to valuesYann Herklotz2020-05-031-0/+9
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* Change to StateYann Herklotz2020-05-031-21/+22
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* Add documentation and conform to specificationYann Herklotz2020-04-291-24/+41
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* Add CompCert semantics for VerilogYann Herklotz2020-04-241-81/+152
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* Add valueToInt functionYann Herklotz2020-04-241-0/+3
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* Add stmnt_runp inductiveYann Herklotz2020-04-221-27/+106
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* Return the actual result of the moduleYann Herklotz2020-04-221-2/+5
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* Remove unnecessary LemmaYann Herklotz2020-04-221-8/+1
| | | | | Still cannot run these functions inside Coq itself, however, they work when they are extracted to Caml.
* Use State in semantics instead of splitting it upYann Herklotz2020-04-221-95/+98
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* Improve printing of resultsYann Herklotz2020-04-222-7/+13
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* Fix Verilog.vYann Herklotz2020-04-171-1/+1
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* Add main module runYann Herklotz2020-04-172-51/+79
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* Fix printing with new Verilog ASTYann Herklotz2020-04-172-26/+54
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* Only generate clocked always blocksYann Herklotz2020-04-171-13/+13
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* Extract simulatorYann Herklotz2020-04-172-5/+5
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* Add Simulator.vYann Herklotz2020-04-171-0/+32
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* Add do notation for optionYann Herklotz2020-04-151-0/+11
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* Make proofs simpler using autoYann Herklotz2020-04-151-59/+45
| | | | | This makes changes to theorems easier, as the proofs will likely not have to be fixed. The runtime is also not much slower.
* Add Verilog semantics with new Verilog moduleYann Herklotz2020-04-151-33/+326
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* Create Value module for bitvectorsYann Herklotz2020-04-151-0/+217
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* Add proof about state wfYann Herklotz2020-04-081-40/+193
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* Add partial proof of well formed stateYann Herklotz2020-04-061-24/+136
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* Fix extraction on linuxYann Herklotz2020-04-021-1/+1
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* Handle loops and conditionals correctlyYann Herklotz2020-04-023-112/+181
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* Complete translation from simple RTL to VerilogYann Herklotz2020-04-011-101/+162
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* Update compilationYann Herklotz2020-04-015-17/+84
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* Convert from RTL to Verilog directlyYann Herklotz2020-03-313-21/+45
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* Add documentation and fix makefile for CompcertYann Herklotz2020-03-315-76/+101
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* Add more operators and print themYann Herklotz2020-03-313-41/+84
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* Use Compcert extractionYann Herklotz2020-03-311-2/+161
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* Improve Verilog error messagesYann Herklotz2020-03-312-2/+11
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