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authorYann Herklotz <git@yannherklotz.com>2021-11-15 21:01:36 +0000
committerYann Herklotz <git@yannherklotz.com>2021-11-15 21:01:36 +0000
commit2f424a8b7b1acd7bbf81c68f64ba2e26bb46b315 (patch)
tree85e1a9608f063dbad3d70f816fbdfabecea12358
parentc54576bce7bccb71a807f8331b9e9d7fbdf1eec3 (diff)
downloadvericert-2f424a8b7b1acd7bbf81c68f64ba2e26bb46b315.tar.gz
vericert-2f424a8b7b1acd7bbf81c68f64ba2e26bb46b315.zip
Use new RAM defined in FunctionalUnits.v
-rw-r--r--src/hls/Memorygen.v5
-rw-r--r--src/hls/Veriloggen.v1
2 files changed, 4 insertions, 2 deletions
diff --git a/src/hls/Memorygen.v b/src/hls/Memorygen.v
index 96c11c3..4ff4a19 100644
--- a/src/hls/Memorygen.v
+++ b/src/hls/Memorygen.v
@@ -35,6 +35,7 @@ Require Import vericert.hls.Verilog.
Require Import vericert.hls.HTL.
Require Import vericert.hls.AssocMap.
Require Import vericert.hls.Array.
+Require Import vericert.hls.FunctionalUnits.
Local Open Scope positive.
Local Open Scope assocmap.
@@ -459,8 +460,8 @@ Lemma forall_ram_lt :
forall_ram (fun x => x < max_reg_module m + 1) r.
Proof.
assert (X: forall a b c, a < b + 1 -> a < Pos.max c b + 1) by lia.
- unfold forall_ram; simplify; unfold max_reg_module; repeat apply X;
- unfold max_reg_ram; rewrite H; try lia.
+ unfold forall_ram; simplify; unfold HTL.max_reg_module; repeat apply X;
+ unfold HTL.max_reg_ram; rewrite H; try lia.
Qed.
#[local] Hint Resolve forall_ram_lt : mgen.
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v
index aba2293..035e7a4 100644
--- a/src/hls/Veriloggen.v
+++ b/src/hls/Veriloggen.v
@@ -25,6 +25,7 @@ Require Import vericert.hls.AssocMap.
Require Import vericert.hls.HTL.
Require Import vericert.hls.ValueInt.
Require Import vericert.hls.Verilog.
+Require Import vericert.hls.FunctionalUnits.
Definition transl_list_fun (a : node * Verilog.stmnt) :=
let (n, stmnt) := a in