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| author | James Pollard <james@pollard.dev> | 2020-05-26 19:50:05 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-05-26 19:50:05 +0100 |
| commit | eaf47a3da2ec43a50bbb92a309c635f4d71347dd (patch) | |
| tree | 9d51a16628a75de426c9f8c1d4c061dcfb9c84dd | |
| parent | 45842fdccf3f2fae7a14508fa939ba2a1cf0d3ce (diff) | |
| download | vericert-eaf47a3da2ec43a50bbb92a309c635f4d71347dd.tar.gz vericert-eaf47a3da2ec43a50bbb92a309c635f4d71347dd.zip | |
Bug fix: stack address normalisation
| -rw-r--r-- | src/translation/Veriloggen.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/translation/Veriloggen.v b/src/translation/Veriloggen.v index e2dc8f4..dcdbaa5 100644 --- a/src/translation/Veriloggen.v +++ b/src/translation/Veriloggen.v @@ -245,7 +245,7 @@ Definition translate_eff_addressing (a: Op.addressing) (args: list reg) : mon ex (* Stack arrays/referenced variables *) | Op.Ainstack a, nil => (* We need to be sure that the base address is aligned *) let a := Integers.Ptrofs.unsigned a in (* FIXME: Assuming stack offsets are +ve; is this ok? *) - if (Z.eq_dec (Z.modulo a 4) 0) then ret (Vlit (ZToValue 32%nat a)) + if (Z.eq_dec (Z.modulo a 4) 0) then ret (Vlit (ZToValue 32%nat (a / 4))) else error (Errors.msg "Veriloggen: eff_addressing misaligned stack offset") | _, _ => error (Errors.msg "Veriloggen: eff_addressing instruction not implemented: other") end. |