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| author | Yann Herklotz <git@yannherklotz.com> | 2022-02-27 12:03:52 +0000 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2022-02-27 12:03:52 +0000 |
| commit | 7dabf0b931036148fd7986d7d75624d81c07f146 (patch) | |
| tree | 2386ef5978acbff5f95e0f63a4042bfd377fce59 /docs/documentation.org | |
| parent | 314e1178ccede8ed42cbfc14b68352a51dcd014b (diff) | |
| download | vericert-7dabf0b931036148fd7986d7d75624d81c07f146.tar.gz vericert-7dabf0b931036148fd7986d7d75624d81c07f146.zip | |
Update documentation generation
Diffstat (limited to 'docs/documentation.org')
| -rw-r--r-- | docs/documentation.org | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/docs/documentation.org b/docs/documentation.org index 3a0633f..e951f83 100644 --- a/docs/documentation.org +++ b/docs/documentation.org @@ -4,7 +4,7 @@ #+email: git@ymhg.org #+language: en -* Docs +* Introduction :PROPERTIES: :EXPORT_FILE_NAME: _index :EXPORT_HUGO_SECTION: docs @@ -15,10 +15,10 @@ Vericert translates C code into a hardware description language called Verilog, synthesised into hardware, to be placed onto a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). -#+attr_html: :width 600 +#+attr_html: :width "600px" #+caption: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language. #+name: fig:design -[[./images/toolflow.svg]] +[[./images/toolflow.png]] The design shown in Figure [[fig:design]] shows how Vericert leverages an existing verified C compiler called [[https://compcert.org/compcert-C.html][CompCert]] to perform this translation. @@ -49,9 +49,9 @@ Free Documentation License''. :END: #+transclude: [[file:~/projects/vericert/README.org::#building][file:~/projects/vericert/README.org::#building]] :only-contents :exclude-elements "headline property-drawer" -#+transclude: [[file:~/projects/vericert/README.org::#downloading-compcert][file:~/projects/vericert/README.org::#downloading-compcert]] -#+transclude: [[file:~/projects/vericert/README.org::#setting-up-nix][file:~/projects/vericert/README.org::#setting-up-nix]] -#+transclude: [[file:~/projects/vericert/README.org::#makefile-build][file:~/projects/vericert/README.org::#makefile-build]] +#+transclude: [[file:~/projects/vericert/README.org::#downloading-compcert][file:~/projects/vericert/README.org::#downloading-compcert]] :level 2 +#+transclude: [[file:~/projects/vericert/README.org::#setting-up-nix][file:~/projects/vericert/README.org::#setting-up-nix]] :level 2 +#+transclude: [[file:~/projects/vericert/README.org::#makefile-build][file:~/projects/vericert/README.org::#makefile-build]] :level 2 ** Testing @@ -155,6 +155,7 @@ to the proper documentation. :PROPERTIES: :CUSTOM_ID: scheduling :END: +#+cindex: scheduling Scheduling is an optimisation which is used to run various instructions in parallel that are independent to each other. |