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| author | Yann Herklotz <git@yannherklotz.com> | 2020-05-04 16:08:43 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-05-04 16:08:43 +0100 |
| commit | dfef69f7844a67210032bfe2597ba5d6b6702469 (patch) | |
| tree | c95e78c006be9e66f96d89f80fd64f7b47fe82dd /example | |
| parent | c106b109fa0d469568c4841f07f7243a4f7813a4 (diff) | |
| download | vericert-dfef69f7844a67210032bfe2597ba5d6b6702469.tar.gz vericert-dfef69f7844a67210032bfe2597ba5d6b6702469.zip | |
Move Verilog to .sv
Diffstat (limited to 'example')
| -rw-r--r-- | example/main.sv (renamed from example/main.v) | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/example/main.v b/example/main.sv index 63130fe..8e97a43 100644 --- a/example/main.v +++ b/example/main.sv @@ -1,6 +1,4 @@ -// -*- mode: verilog -*- - -module main(input start, reset, clk, +module main(input start, reset, clk, output finished, output [31:0] return_val); reg [31:0] x; |