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author | Yann Herklotz <git@yannherklotz.com> | 2021-11-18 22:14:30 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-11-18 22:14:30 +0000 |
commit | 3c5bd88f22f744e4908afbc5a56e202dfa469360 (patch) | |
tree | 57ddb252b09bdc61665fcab97ff169acc9af23e7 /scripts | |
parent | e6348c97faee39754efd13b69a70c54851e2a789 (diff) | |
download | vericert-3c5bd88f22f744e4908afbc5a56e202dfa469360.tar.gz vericert-3c5bd88f22f744e4908afbc5a56e202dfa469360.zip |
Fix compilation with new HTL language
Diffstat (limited to 'scripts')
-rw-r--r-- | scripts/synth.tcl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/scripts/synth.tcl b/scripts/synth.tcl index e5151e8..a2fb722 100644 --- a/scripts/synth.tcl +++ b/scripts/synth.tcl @@ -76,7 +76,7 @@ proc dump_statistics { } { }; #END PROC set outputDir . create_project -in_memory -part xc7z020clg484-1 -force -read_verilog main.v +read_verilog -sv main.v synth_design -mode out_of_context -no_iobuf -top main -part xc7z020clg484-1 write_checkpoint -force $outputDir/post_synth.dcp report_timing_summary -file $outputDir/post_synth_timing_summary.rpt |