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| author | Yann Herklotz <git@yannherklotz.com> | 2020-12-17 10:04:21 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-12-17 10:04:21 +0000 |
| commit | 8a0bd7b74939b65a89b81352b238d1d8252fb278 (patch) | |
| tree | bd6a099b74e2035da32fe963c688c907f9c46722 /src/Compiler.v | |
| parent | fd52cc1edbe192e3a4b6e6780be8761d5702664b (diff) | |
| download | vericert-8a0bd7b74939b65a89b81352b238d1d8252fb278.tar.gz vericert-8a0bd7b74939b65a89b81352b238d1d8252fb278.zip | |
Add extraction and loop pipelining stage
Diffstat (limited to 'src/Compiler.v')
| -rw-r--r-- | src/Compiler.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 7df00d8..5895e1d 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -74,7 +74,8 @@ From vericert Require HTLgen RTLBlock RTLBlockgen - HTLSchedulegen. + HTLSchedulegen + Pipeline. From compcert Require Import Smallstep. @@ -240,6 +241,8 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := @@ print (print_RTL 6) @@@ time "Unused globals" Unusedglob.transform_program @@ print (print_RTL 7) + @@ Pipeline.transf_program + @@ print (print_RTL 8) @@@ RTLBlockgen.transl_program @@ print print_RTLBlock @@@ HTLSchedulegen.transl_program |