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| author | Yann Herklotz <git@yannherklotz.com> | 2020-03-31 19:40:42 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-03-31 19:40:42 +0100 |
| commit | 40df7e29e263a5dad8fb894f2d39753d750ac8e3 (patch) | |
| tree | aac4d5c528e9f1389f79540ea94d55f3af11c920 /src/extraction | |
| parent | 0b4808a3705317c96387de036381e4e6add4e956 (diff) | |
| download | vericert-40df7e29e263a5dad8fb894f2d39753d750ac8e3.tar.gz vericert-40df7e29e263a5dad8fb894f2d39753d750ac8e3.zip | |
Convert from RTL to Verilog directly
Diffstat (limited to 'src/extraction')
| -rw-r--r-- | src/extraction/Extraction.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index e71721e..4403019 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -126,12 +126,15 @@ Extract Constant Compopts.debug => (* Compiler *) Extract Constant Compiler.print_Clight => "PrintClight.print_if". Extract Constant Compiler.print_Cminor => "PrintCminor.print_if". +Extract Constant driver.Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_LTL => "PrintLTL.print_if". Extract Constant Compiler.print_Mach => "PrintMach.print_if". Extract Constant Compiler.print => "fun (f: 'a -> unit) (x: 'a) -> f x; x". Extract Constant Compiler.time => "Timing.time_coq". +Extract Constant Coquplib.debug_print => "print_newline". + (*Extraction Inline Compiler.apply_total Compiler.apply_partial.*) (* Cabs *) |