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| author | Yann Herklotz <git@yannherklotz.com> | 2021-02-15 00:06:29 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-02-15 00:06:29 +0000 |
| commit | 171b326ade18ab77eb155a9d203f2f523708b29b (patch) | |
| tree | df9f02bc68c7dc539a67ac376ad7a5d4435c07c3 /src/hls/HTLgen.v | |
| parent | 5f1e7aa8fbc4a0e04d0b137410c13f3d8da4d987 (diff) | |
| download | vericert-171b326ade18ab77eb155a9d203f2f523708b29b.tar.gz vericert-171b326ade18ab77eb155a9d203f2f523708b29b.zip | |
Add beginning to scheduling division
Diffstat (limited to 'src/hls/HTLgen.v')
| -rw-r--r-- | src/hls/HTLgen.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/hls/HTLgen.v b/src/hls/HTLgen.v index f1e6b2a..b323a65 100644 --- a/src/hls/HTLgen.v +++ b/src/hls/HTLgen.v @@ -610,6 +610,7 @@ Definition transf_module (f: function) : mon HTL.module := start rst clk + nil current_state.(st_scldecls) current_state.(st_arrdecls) (conj (max_pc_wf _ LECTRL) (max_pc_wf _ LEDATA))) |