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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:33 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:33 +0000 |
| commit | 05347ca5126f335b0479b71a4576b141e082fab5 (patch) | |
| tree | b4dc63f00ca3b8158ad11ea77fafd4cec382c95f /src/hls/HTLgenspec.v | |
| parent | 8ddf6a9ff669fbc28cb3247c6ce40cb8fa4cc3fc (diff) | |
| download | vericert-05347ca5126f335b0479b71a4576b141e082fab5.tar.gz vericert-05347ca5126f335b0479b71a4576b141e082fab5.zip | |
Add RAM to HTL
Diffstat (limited to 'src/hls/HTLgenspec.v')
| -rw-r--r-- | src/hls/HTLgenspec.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/HTLgenspec.v b/src/hls/HTLgenspec.v index 845b1d5..7cb6d8c 100644 --- a/src/hls/HTLgenspec.v +++ b/src/hls/HTLgenspec.v @@ -183,7 +183,7 @@ Inductive tr_module (f : RTL.function) : module -> Prop := data control f.(RTL.fn_entrypoint) - st stk stk_len fin rtrn start rst clk scldecls arrdecls wf) -> + st stk stk_len fin rtrn start rst clk scldecls arrdecls None wf) -> (forall pc i, Maps.PTree.get pc f.(RTL.fn_code) = Some i -> tr_code f.(RTL.fn_code) pc i data control fin rtrn st stk) -> stk_len = Z.to_nat (f.(RTL.fn_stacksize) / 4) -> |