diff options
author | Yann Herklotz <git@yannherklotz.com> | 2021-02-21 21:35:34 +0000 |
---|---|---|
committer | Yann Herklotz <git@yannherklotz.com> | 2021-02-21 21:35:34 +0000 |
commit | 359194617de51adcc451b45b6c1b0a9332820906 (patch) | |
tree | 7b1fce73244ebbb1195c37dd986de0bf1d081a0c /src/hls/PrintVerilog.ml | |
parent | a47cfd17f0e1fc6aca5e10de9362a4be2d4af468 (diff) | |
download | vericert-359194617de51adcc451b45b6c1b0a9332820906.tar.gz vericert-359194617de51adcc451b45b6c1b0a9332820906.zip |
Add new instructions for pipelines
Diffstat (limited to 'src/hls/PrintVerilog.ml')
-rw-r--r-- | src/hls/PrintVerilog.ml | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 8c9f20e..824623e 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -257,7 +257,9 @@ let pprint_module debug i n m = concat [ indent i; "module "; (extern_atom n); "("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n"; fold_map (pprint_module_item (i+1)) m.mod_body; - concat (List.map (print_funct_units m.mod_clk) m.mod_funct_units); + concat (List.map (print_funct_units m.mod_clk) + (Maps.PTree.elements m.mod_funct_units.avail_units + |> List.map snd)); if !option_initial then print_initial i (Nat.to_int m.mod_stk_len) m.mod_stk else ""; if debug then debug_always_verbose i m.mod_clk m.mod_st else ""; indent i; "endmodule\n\n" |