diff options
| author | Yann Herklotz <git@yannherklotz.com> | 2021-02-22 19:04:52 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-02-22 19:04:52 +0000 |
| commit | 75641815724c68791cc2754e850b35700e07e586 (patch) | |
| tree | 8a47101dd7d01d80e90ce18a265aced7e4a82058 /src/hls/PrintVerilog.ml | |
| parent | b34a08dd656664352e400379d2e890ad95e3afc2 (diff) | |
| download | vericert-75641815724c68791cc2754e850b35700e07e586.tar.gz vericert-75641815724c68791cc2754e850b35700e07e586.zip | |
Get some Verilog output with dividersdev/divider
Diffstat (limited to 'src/hls/PrintVerilog.ml')
| -rw-r--r-- | src/hls/PrintVerilog.ml | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 824623e..da3bd6e 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -178,11 +178,15 @@ let make_io i io r = concat [indent i; io; " "; register r; ";\n"] let print_funct_units clk = function | SignedDiv (stages, numer, denom, quot, rem) -> - sprintf "div_signed #(.stages(%d)) divs(.clk(%s), .clken(1'b1), .numer(%s), .denom(%s), .quotient(%s), .remain(%s))\n" + sprintf ("div_signed #(.stages(%d)) divs(.clk(%s), " ^^ + ".clken(1'b1), .numer(%s), .denom(%s), " ^^ + ".quotient(%s), .remain(%s))\n") (P.to_int stages) (register clk) (register numer) (register denom) (register quot) (register rem) | UnsignedDiv (stages, numer, denom, quot, rem) -> - sprintf "div_unsigned #(.stages(%d)) divs(.clk(%s), .clken(1'b1), .numer(%s), .denom(%s), .quotient(%s), .remain(%s))\n" + sprintf ("div_unsigned #(.stages(%d)) divs(.clk(%s), " ^^ + ".clken(1'b1), .numer(%s), .denom(%s), " ^^ + ".quotient(%s), .remain(%s))\n") (P.to_int stages) (register clk) (register numer) (register denom) (register quot) (register rem) |