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| author | Yann Herklotz <git@yannherklotz.com> | 2020-10-23 13:25:10 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-10-23 13:25:10 +0100 |
| commit | e1b64efcb01015987763b94a21439ded9817b6b6 (patch) | |
| tree | 653107c502789a48ad4021bf5b56083443c84cc7 /src/hls/PrintVerilog.ml | |
| parent | b8e2a41b7023954f7de91c9d3835804a11908386 (diff) | |
| download | vericert-e1b64efcb01015987763b94a21439ded9817b6b6.tar.gz vericert-e1b64efcb01015987763b94a21439ded9817b6b6.zip | |
Fix printing of negative numbers
Diffstat (limited to 'src/hls/PrintVerilog.ml')
| -rw-r--r-- | src/hls/PrintVerilog.ml | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 0f64066..353bfac 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -72,7 +72,11 @@ let register a = sprintf "reg_%d" (P.to_int a) (*let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l))*) -let literal l = sprintf "32'd%ld" (camlint_of_coqint l) +let literal l = + let l' = camlint_of_coqint l in + if l' < Int32.zero + then sprintf "(- 32'd%ld)" (Int32.neg l') + else sprintf "32'd%ld" l' let rec pprint_expr = function | Vlit l -> literal l |