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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:26:45 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:26:45 +0000 |
| commit | d6cfa2f23ddbc83340386c3111f33740ea0cbdeb (patch) | |
| tree | 8db5eaff4d6dff4845a0473e9bf2800661c8dafe /src/hls/PrintVerilog.ml | |
| parent | 5b2e88abeb23ac8b6e570e8c80422e3635088891 (diff) | |
| download | vericert-d6cfa2f23ddbc83340386c3111f33740ea0cbdeb.tar.gz vericert-d6cfa2f23ddbc83340386c3111f33740ea0cbdeb.zip | |
Print Verilog in reverse order
Diffstat (limited to 'src/hls/PrintVerilog.ml')
| -rw-r--r-- | src/hls/PrintVerilog.ml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 3817fd3..d076386 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -247,7 +247,7 @@ let pprint_module debug i n m = ]; concat [ indent i; "module "; (extern_atom n); "("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n"; - fold_map (pprint_module_item (i+1)) m.mod_body; + fold_map (pprint_module_item (i+1)) (List.rev m.mod_body); if !option_initial then print_initial i (Nat.to_int m.mod_stk_len) m.mod_stk else ""; if debug then debug_always_verbose i m.mod_clk m.mod_st else ""; indent i; "endmodule\n\n" |