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authorYann Herklotz <git@yannherklotz.com>2023-08-10 12:29:11 +0100
committerYann Herklotz <git@yannherklotz.com>2023-08-10 12:29:11 +0100
commit533bca9426ee3166433b29e84c8f942f7409981b (patch)
tree5bfad6d46b06ace593ed7e55da60bf34b8943b67 /src/hls/Verilog.v
parentf6569b736d4ded08a011f55bd6001c89e899fd5c (diff)
downloadvericert-dev/asplos.tar.gz
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Annonimize submissiondev/asplos
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-rw-r--r--src/hls/Verilog.v4
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diff --git a/src/hls/Verilog.v b/src/hls/Verilog.v
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--- a/src/hls/Verilog.v
+++ b/src/hls/Verilog.v
@@ -1,7 +1,7 @@
(*
* Vericert: Verified high-level synthesis.
- * Copyright (C) 2019-2020 Yann Herklotz <yann@yannherklotz.com>
- * 2020 James Pollard <j@mes.dev>
+ * Copyright (C) 2019-2020 ___ ___ <___@______.com>
+ * 2020 ___ ___ <___>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by