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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-31 20:45:15 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-31 20:45:15 +0100 |
| commit | 2837868fcc427b2161b083f33d3de495f0c21bf7 (patch) | |
| tree | af64714106456b6c5afb28835735a75e634754a8 /src/hls/Veriloggen.v | |
| parent | ff10c279b5ddbac503ed0da1f1e0c25cd0979749 (diff) | |
| download | vericert-2837868fcc427b2161b083f33d3de495f0c21bf7.tar.gz vericert-2837868fcc427b2161b083f33d3de495f0c21bf7.zip | |
Add memory disable
Diffstat (limited to 'src/hls/Veriloggen.v')
| -rw-r--r-- | src/hls/Veriloggen.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index 776f17f..108e816 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -44,13 +44,15 @@ Definition arr_to_Vdeclarr arrdecl := map arr_to_Vdeclarr_fun arrdecl. Definition inst_ram clk stk_len ram := Valways (Vnegedge clk) - (Vcond (Vbinop Vand (Vvar (ram_en ram)) (Vbinop Vlt (Vvar (ram_addr ram)) (Vlit (natToValue stk_len)))) + (Vseq (Vcond (Vbinop Vand (Vvar (ram_en ram)) + (Vbinop Vlt (Vvar (ram_addr ram)) (Vlit (natToValue stk_len)))) (Vcond (Vvar (ram_wr_en ram)) (Vnonblock (Vvari (ram_mem ram) (Vvar (ram_addr ram))) (Vvar (ram_d_in ram))) (Vnonblock (Vvar (ram_d_out ram)) (Vvari (ram_mem ram) (Vvar (ram_addr ram))))) - Vskip). + Vskip) + (Vnonblock (Vvar (ram_en ram)) (Vlit (ZToValue 0)))). Definition transl_module (m : HTL.module) : Verilog.module := let case_el_ctrl := list_to_stmnt (transl_list (PTree.elements m.(mod_controllogic))) in |