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| author | Yann Herklotz <git@yannherklotz.com> | 2021-11-18 22:14:30 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-11-18 22:14:30 +0000 |
| commit | 3c5bd88f22f744e4908afbc5a56e202dfa469360 (patch) | |
| tree | 57ddb252b09bdc61665fcab97ff169acc9af23e7 /src/hls/Veriloggen.v | |
| parent | e6348c97faee39754efd13b69a70c54851e2a789 (diff) | |
| download | vericert-3c5bd88f22f744e4908afbc5a56e202dfa469360.tar.gz vericert-3c5bd88f22f744e4908afbc5a56e202dfa469360.zip | |
Fix compilation with new HTL language
Diffstat (limited to 'src/hls/Veriloggen.v')
| -rw-r--r-- | src/hls/Veriloggen.v | 31 |
1 files changed, 5 insertions, 26 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index 035e7a4..c07e18d 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -57,9 +57,8 @@ Definition inst_ram clk ram := Definition transl_module (m : HTL.module) : Verilog.module := let case_el_ctrl := list_to_stmnt (transl_list (PTree.elements m.(mod_controllogic))) in let case_el_data := list_to_stmnt (transl_list (PTree.elements m.(mod_datapath))) in - match m.(HTL.mod_ram) with - | Some ram => - let body := + let ram := m.(HTL.mod_ram) in + let body := Valways (Vposedge m.(HTL.mod_clk)) (Vcond (Vbinop Veq (Vvar m.(HTL.mod_reset)) (Vlit (ZToValue 1))) (Vnonblock (Vvar m.(HTL.mod_st)) (Vlit (posToValue m.(HTL.mod_entrypoint)))) (Vcase (Vvar m.(HTL.mod_st)) case_el_ctrl (Some Vskip))) @@ -73,31 +72,11 @@ Definition transl_module (m : HTL.module) : Verilog.module := m.(HTL.mod_finish) m.(HTL.mod_return) m.(HTL.mod_st) - m.(HTL.mod_stk) - m.(HTL.mod_stk_len) + m.(HTL.mod_ram).(ram_mem) + m.(HTL.mod_ram).(ram_size) m.(HTL.mod_params) body - m.(HTL.mod_entrypoint) - | None => - let body := - Valways (Vposedge m.(HTL.mod_clk)) (Vcond (Vbinop Veq (Vvar m.(HTL.mod_reset)) (Vlit (ZToValue 1))) - (Vnonblock (Vvar m.(HTL.mod_st)) (Vlit (posToValue m.(HTL.mod_entrypoint)))) - (Vcase (Vvar m.(HTL.mod_st)) case_el_ctrl (Some Vskip))) - :: Valways (Vposedge m.(HTL.mod_clk)) (Vcase (Vvar m.(HTL.mod_st)) case_el_data (Some Vskip)) - :: List.map Vdeclaration (arr_to_Vdeclarr (AssocMap.elements m.(mod_arrdecls)) - ++ scl_to_Vdecl (AssocMap.elements m.(mod_scldecls))) in - Verilog.mkmodule m.(HTL.mod_start) - m.(HTL.mod_reset) - m.(HTL.mod_clk) - m.(HTL.mod_finish) - m.(HTL.mod_return) - m.(HTL.mod_st) - m.(HTL.mod_stk) - m.(HTL.mod_stk_len) - m.(HTL.mod_params) - body - m.(HTL.mod_entrypoint) - end. + m.(HTL.mod_entrypoint). Definition transl_fundef := transf_fundef transl_module. |