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| author | Michalis Pardalos <m.pardalos@gmail.com> | 2021-03-01 11:16:33 +0000 |
|---|---|---|
| committer | Michalis Pardalos <m.pardalos@gmail.com> | 2021-03-01 11:16:33 +0000 |
| commit | dc518898cac3b8e06684b6e66377d430ab30a52e (patch) | |
| tree | f7e955965d26324f6ac594c8197c472e2dc61541 /src/hls/Veriloggen.v | |
| parent | ef205f12c75891be73d221995946df441d143791 (diff) | |
| download | vericert-dc518898cac3b8e06684b6e66377d430ab30a52e.tar.gz vericert-dc518898cac3b8e06684b6e66377d430ab30a52e.zip | |
Typos in Veriloggen
Diffstat (limited to 'src/hls/Veriloggen.v')
| -rw-r--r-- | src/hls/Veriloggen.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index 83f7abe..2ced686 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -112,7 +112,7 @@ Section RENUMBER. ret (Vbinop op e1' e2') | Vunop op e => do e' <- renumber_expr e; - ret (Vunop op e) + ret (Vunop op e') | Vternary e1 e2 e3 => do e1' <- renumber_expr e1; do e2' <- renumber_expr e2; @@ -122,7 +122,7 @@ Section RENUMBER. do e1' <- renumber_expr e1; do e2' <- renumber_expr e2; do r' <- renumber_reg r; - ret (Vrange r e1 e2) + ret (Vrange r e1' e2') end. Fixpoint renumber_stmnt (stmnt : Verilog.stmnt) := |