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| author | Yann Herklotz <git@yannherklotz.com> | 2020-07-24 10:22:13 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-07-24 10:22:13 +0100 |
| commit | 5cf10a4c70763cbb95747b19ac35b57a9dee4dd5 (patch) | |
| tree | eeb5a90e4d651093ac27058d4e83775a37ae1348 /src/verilog/PrintVerilog.ml | |
| parent | 1cc5a458f28ad44919c9bfafbd5191c253e453e2 (diff) | |
| download | vericert-5cf10a4c70763cbb95747b19ac35b57a9dee4dd5.tar.gz vericert-5cf10a4c70763cbb95747b19ac35b57a9dee4dd5.zip | |
More renames to get it to compile
Diffstat (limited to 'src/verilog/PrintVerilog.ml')
| -rw-r--r-- | src/verilog/PrintVerilog.ml | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index f348ee6..0f64066 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -17,7 +17,7 @@ *) open Verilog -open Value +open ValueInt open Datatypes open Camlcoq @@ -70,7 +70,9 @@ let unop = function let register a = sprintf "reg_%d" (P.to_int a) -let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l)) +(*let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l))*) + +let literal l = sprintf "32'd%ld" (camlint_of_coqint l) let rec pprint_expr = function | Vlit l -> literal l |