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| author | James Pollard <james@pollard.dev> | 2020-06-03 17:31:35 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-06-03 17:31:35 +0100 |
| commit | e3c66ff88570c5370b37f51404f71f485d2e5dfe (patch) | |
| tree | 87168bb6494adf1c11d0e569f86634a42beb0ae7 /src/verilog | |
| parent | 6bb3ff9cd85a52cd7c6509515a5e9f05bd0bb16f (diff) | |
| download | vericert-e3c66ff88570c5370b37f51404f71f485d2e5dfe.tar.gz vericert-e3c66ff88570c5370b37f51404f71f485d2e5dfe.zip | |
HTLgenspec status in line with develop
Diffstat (limited to 'src/verilog')
| -rw-r--r-- | src/verilog/HTL.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index a553453..cb081b2 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -43,6 +43,7 @@ Record module: Type := mod_controllogic : controllogic; mod_entrypoint : node; mod_st : reg; + mod_stk : reg; mod_finish : reg; mod_return : reg }. |