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| author | Yann Herklotz <git@yannherklotz.com> | 2020-07-24 10:22:13 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-07-24 10:22:13 +0100 |
| commit | 5cf10a4c70763cbb95747b19ac35b57a9dee4dd5 (patch) | |
| tree | eeb5a90e4d651093ac27058d4e83775a37ae1348 /src | |
| parent | 1cc5a458f28ad44919c9bfafbd5191c253e453e2 (diff) | |
| download | vericert-5cf10a4c70763cbb95747b19ac35b57a9dee4dd5.tar.gz vericert-5cf10a4c70763cbb95747b19ac35b57a9dee4dd5.zip | |
More renames to get it to compile
Diffstat (limited to 'src')
| -rw-r--r-- | src/VericertClflags.ml (renamed from src/CoqupClflags.ml) | 0 | ||||
| -rw-r--r-- | src/translation/HTLgenproof.v | 5 | ||||
| -rw-r--r-- | src/verilog/PrintVerilog.ml | 6 | ||||
| -rw-r--r-- | src/verilog/PrintVerilog.mli | 4 |
4 files changed, 9 insertions, 6 deletions
diff --git a/src/CoqupClflags.ml b/src/VericertClflags.ml index ca591de..ca591de 100644 --- a/src/CoqupClflags.ml +++ b/src/VericertClflags.ml diff --git a/src/translation/HTLgenproof.v b/src/translation/HTLgenproof.v index ddf8c3a..b1cf958 100644 --- a/src/translation/HTLgenproof.v +++ b/src/translation/HTLgenproof.v @@ -577,7 +577,7 @@ Section CORRECTNESS. - pose proof Integers.Ptrofs.agree32_sub as AGR; unfold Integers.Ptrofs.agree32 in AGR. assert (ARCH: Archi.ptr64 = false) by auto. eapply AGR in ARCH. apply int_inj. unfold Ptrofs.to_int. rewrite Int.unsigned_repr. - apply ARCH. Search Ptrofs.unsigned. pose proof Ptrofs.unsigned_range_2. + apply ARCH. pose proof Ptrofs.unsigned_range_2. replace Ptrofs.max_unsigned with Int.max_unsigned; auto. pose proof Ptrofs.agree32_of_int. unfold Ptrofs.agree32 in H2. eapply H2 in ARCH. apply ARCH. @@ -708,12 +708,13 @@ Section CORRECTNESS. Admitted. Lemma eval_cond_correct : + forall e asa asr f' m args rs cond, exists v' : value, Verilog.expr_runp f' asr asa e v' /\ val_value_lessdef (Values.Val.of_optbool (Op.eval_condition cond - (map (fun r : positive => Registers.Regmap.get r rs) args) m)) v' + (map (fun r : positive => Registers.Regmap.get r rs) args) m)) v'. Admitted. (** The proof of semantic preservation for the translation of instructions diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index f348ee6..0f64066 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -17,7 +17,7 @@ *) open Verilog -open Value +open ValueInt open Datatypes open Camlcoq @@ -70,7 +70,9 @@ let unop = function let register a = sprintf "reg_%d" (P.to_int a) -let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l)) +(*let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l))*) + +let literal l = sprintf "32'd%ld" (camlint_of_coqint l) let rec pprint_expr = function | Vlit l -> literal l diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 47af3ef..6a15ee9 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -18,8 +18,8 @@ val pprint_stmnt : int -> Verilog.stmnt -> string -val print_value : out_channel -> Value.value -> unit +val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit -val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit +val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit |