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| author | Yann Herklotz <git@yannherklotz.com> | 2022-05-31 02:06:44 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2022-05-31 02:06:44 +0100 |
| commit | 7464314d55ee6401f93472e985e5836393a89b46 (patch) | |
| tree | cb4944396b76a599575b9c0fb7617d645d9a0a7d /src | |
| parent | 5c8b41b60e8f943632d666c6566c83a9ea74c8a4 (diff) | |
| download | vericert-7464314d55ee6401f93472e985e5836393a89b46.tar.gz vericert-7464314d55ee6401f93472e985e5836393a89b46.zip | |
Place both case statements into the same always block
Diffstat (limited to 'src')
| -rw-r--r-- | src/hls/Veriloggen.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index c07e18d..fe8e90c 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -59,10 +59,11 @@ Definition transl_module (m : HTL.module) : Verilog.module := let case_el_data := list_to_stmnt (transl_list (PTree.elements m.(mod_datapath))) in let ram := m.(HTL.mod_ram) in let body := - Valways (Vposedge m.(HTL.mod_clk)) (Vcond (Vbinop Veq (Vvar m.(HTL.mod_reset)) (Vlit (ZToValue 1))) - (Vnonblock (Vvar m.(HTL.mod_st)) (Vlit (posToValue m.(HTL.mod_entrypoint)))) - (Vcase (Vvar m.(HTL.mod_st)) case_el_ctrl (Some Vskip))) - :: Valways (Vposedge m.(HTL.mod_clk)) (Vcase (Vvar m.(HTL.mod_st)) case_el_data (Some Vskip)) + Valways (Vposedge m.(HTL.mod_clk)) + (Vseq (Vcase (Vvar m.(HTL.mod_st)) case_el_data (Some Vskip)) + (Vcond (Vbinop Veq (Vvar m.(HTL.mod_reset)) (Vlit (ZToValue 1))) + (Vblock (Vvar m.(HTL.mod_st)) (Vlit (posToValue m.(HTL.mod_entrypoint)))) + (Vcase (Vvar m.(HTL.mod_st)) case_el_ctrl (Some Vskip)))) :: inst_ram m.(HTL.mod_clk) ram :: List.map Vdeclaration (arr_to_Vdeclarr (AssocMap.elements m.(mod_arrdecls)) ++ scl_to_Vdecl (AssocMap.elements m.(mod_scldecls))) in |