Print instantiations in HTL output

3 files changed, 29 insertions, 14 deletions

diff --git a/src/verilog/PrintHTL.ml b/src/verilog/PrintHTL.ml
index 44f8b01..10b35b5 100644
--- a/src/verilog/PrintHTL.ml
+++ b/src/verilog/PrintHTL.ml
@@ -42,21 +42,27 @@ let rec regs pp = function
 let print_instruction pp (pc, i) =
   fprintf pp "%5d:\t%s" pc (pprint_stmnt 0 i)
 
+let print_instance pp (pc, i) =
+  fprintf pp "%5d:\t%s" pc (pprint_instantiation i)
+
+let ptree_to_list ptree =
+  List.sort
+    (fun (pc1, _) (pc2, _) -> compare pc2 pc1)
+    (List.rev_map
+      (fun (pc, i) -> (P.to_int pc, i))
+      (PTree.elements ptree))
+
 let print_module pp id f =
   fprintf pp "%s(%a) {\n" (extern_atom id) regs f.mod_params;
-  let datapath =
-    List.sort
-      (fun (pc1, _) (pc2, _) -> compare pc2 pc1)
-      (List.rev_map
-        (fun (pc, i) -> (P.to_int pc, i))
-        (PTree.elements f.mod_datapath)) in
-  let controllogic =
-    List.sort
-      (fun (pc1, _) (pc2, _) -> compare pc2 pc1)
-      (List.rev_map
-        (fun (pc, i) -> (P.to_int pc, i))
-        (PTree.elements f.mod_controllogic)) in
-  fprintf pp "  datapath {\n";
+  let datapath = ptree_to_list f.mod_datapath in
+  let controllogic = ptree_to_list f.mod_controllogic in
+  let insts = ptree_to_list f.mod_insts in
+  if List.length insts > 0 then (
+    fprintf pp "  instances {\n";
+    List.iter (print_instance pp) insts;
+    fprintf pp "  }\n\n";
+  ) else fprintf pp "  ";
+  fprintf pp "datapath {\n";
   List.iter (print_instruction pp) datapath;
   fprintf pp "  }\n\n  controllogic {\n";
   List.iter (print_instruction pp) controllogic;
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index 39aa053..da4dd5d 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -74,7 +74,7 @@ let unop = function
   | Vnot -> " ! "
 
 let register a = sprintf "reg_%d" (P.to_int a)
-let vmodule a = sprintf "module_%d" (P.to_int a)
+let vmodule a = sprintf "%s" (extern_atom a)
 let instance a = sprintf "instance_%d" (P.to_int a)
 
 (*let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l))*)
@@ -109,6 +109,13 @@ let rec pprint_stmnt i =
   | Vblock (a, b) -> concat [indent i; pprint_expr a; " = "; pprint_expr b; ";\n"]
   | Vnonblock (a, b) -> concat [indent i; pprint_expr a; " <= "; pprint_expr b; ";\n"]
 
+let pprint_instantiation = function
+  | Vinstantiation (m, name, args) -> concat [
+      vmodule m; " ";
+      instance name; "("; concat (intersperse ", " (List.map register args)); ")";
+      ";\n"
+    ]
+
 let rec pprint_edge = function
   | Vposedge r -> concat ["posedge "; register r]
   | Vnegedge r -> concat ["negedge "; register r]
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli
index 6a15ee9..1a37126 100644
--- a/src/verilog/PrintVerilog.mli
+++ b/src/verilog/PrintVerilog.mli
@@ -18,6 +18,8 @@
 
 val pprint_stmnt : int -> Verilog.stmnt -> string
 
+val pprint_instantiation : Verilog.instantiation -> string
+
 val print_value : out_channel -> ValueInt.value -> unit
 
 val print_program : bool -> out_channel -> Verilog.program -> unit