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authorYann Herklotz <git@yannherklotz.com>2022-05-31 02:07:01 +0100
committerYann Herklotz <git@yannherklotz.com>2022-05-31 02:07:01 +0100
commita8aef8ab043500f10cfb82ee5d86efedba50cae4 (patch)
tree6301daa3298f73b80eea48d0c0487ddb20005e7e /test
parent7464314d55ee6401f93472e985e5836393a89b46 (diff)
downloadvericert-a8aef8ab043500f10cfb82ee5d86efedba50cae4.tar.gz
vericert-a8aef8ab043500f10cfb82ee5d86efedba50cae4.zip
Use the .sv extension for Verilog
Diffstat (limited to 'test')
-rw-r--r--test/Makefile6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/Makefile b/test/Makefile
index aa76e70..58a3c12 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -17,10 +17,10 @@ all: $(TESTS)
%.gcc: %.o
@$(CC) $(CFLAGS) -o $@ $<
-%.v: %.c
+%.sv: %.c
$(VERICERT) $(VERICERT_OPTS) -o $@ $<
-%.iver: %.v
+%.iver: %.sv
@$(IVERILOG) $(IVERILOG_OPTS) -o $@ -- $<
%.veri.out: %.iver
@@ -31,4 +31,4 @@ all: $(TESTS)
@printf "\033[0;36mOK\033[0m\t$(patsubst %.check,%,$@)\n"
clean:
- rm -f *.check *.gcc *.gcc.out *.o *.v *.iver *.veri.out
+ rm -f *.check *.gcc *.gcc.out *.o *.sv *.iver *.veri.out