diff options
| -rw-r--r-- | src/hls/PrintVerilog.ml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 2e0f0e1..a096bd1 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -28,7 +28,7 @@ open Clflags open Printf open VericertClflags -open FunctionalUnits +(* open FunctionalUnits *) module PMap = Map.Make (struct type t = P.t |