1 files changed, 46 insertions, 0 deletions
diff --git a/scripts/run-vericert.sh b/scripts/run-vericert.sh
new file mode 100755
index 0000000..9deaa10
--- /dev/null
+++ b/scripts/run-vericert.sh
@@ -0,0 +1,46 @@
+#!/usr/bin/env bash
+
+rm exec.csv
+
+top=$(pwd)
+#set up
+while read benchmark ; do
+   printf "%10s\t" $(echo "$benchmark" | sed -e 's|/| |g')
+   ./$benchmark.gcc > $benchmark.clog
+   cresult=$(cat $benchmark.clog | cut -d' ' -f2)
+   #echo "C output: "$cresult
+   #./$benchmark.iver > $benchmark.tmp
+   if [[ ! -f ./$benchmark.verilator/Vmain ]]; then
+      echo -e "\e[0;91mFAIL\e[0m: Verilog failed compilation"
+      continue
+   fi
+   ./$benchmark.verilator/Vmain > $benchmark.tmp
+   veriresult=$(tail -1 $benchmark.tmp | cut -d' ' -f2)
+   cycles=$(tail -2 $benchmark.tmp | head -1 | tr -s ' ' | cut -d' ' -f2)
+   #echo "Verilog output: "$veriresult
+
+   #Undefined checks
+   if [[ -z "$veriresult" ]]
+   then
+      echo "\e[0;91mFAIL\e[0m: Verilog returned nothing"
+      #exit 0
+   fi
+   
+   # Don't care checks
+   if [[ $veriresult == "x" ]]
+   then
+      echo "\e[0;91mFAIL\e[0m: Verilog returned don't cares"
+      #exit 0
+   fi
+
+   # unequal result check
+   if [[ $cresult -ne $veriresult ]]
+   then 
+      echo -e "\e[0;91mFAIL\e[0m: Verilog and C output do not match!"
+      #exit 0
+   else 
+      echo -e "\e[0;92mPASS\e[0m"
+   fi
+   name=$(echo $benchmark | awk -v FS="/" '{print $NF}')
+   echo $name","$cycles >> exec.csv
+done < benchmark-list-master