diff options
Diffstat (limited to 'src/extraction/Extraction.v')
| -rw-r--r-- | src/extraction/Extraction.v | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 5c1dac5..bca8fb5 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -25,7 +25,9 @@ From vericert Require RTLBlockInstr HTLgen Pipeline - HLSOpts. + HLSOpts + Predicate +. From Coq Require DecidableClass. @@ -134,6 +136,8 @@ Extract Constant Compopts.debug => Extract Constant HLSOpts.optim_if_conversion => "fun _ -> !VericertClflags.option_fif_conv". +Extract Constant HLSOpts.optim_ram => + "fun _ -> !VericertClflags.option_fram". (* Compiler *) Extract Constant Compiler.print_Clight => "PrintClight.print_if". @@ -143,6 +147,7 @@ Extract Constant Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_RTLBlock => "PrintRTLBlock.print_if". Extract Constant Compiler.print_RTLPar => "PrintRTLPar.print_if". Extract Constant Compiler.print_HTL => "PrintHTL.print_if". +Extract Constant Compiler.print_RTLPar => "PrintRTLPar.print_if". Extract Constant Compiler.print_LTL => "PrintLTL.print_if". Extract Constant Compiler.print_Mach => "PrintMach.print_if". Extract Constant Compiler.print => "fun (f: 'a -> unit) (x: 'a) -> f x; x". @@ -190,7 +195,8 @@ Separate Extraction RTLBlockgen.transl_program RTLBlockInstr.successors_instr HTLgen.tbl_to_case_expr Pipeline.pipeline - RTLBlockInstr.sat_pred_temp + Predicate.sat_pred_simple + Verilog.stmnt_to_list Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state |