diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/hls/PrintHTL.ml | 16 | ||||
| -rw-r--r-- | src/hls/PrintVerilog.mli | 2 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/hls/PrintHTL.ml b/src/hls/PrintHTL.ml index d051aad..3bce337 100644 --- a/src/hls/PrintHTL.ml +++ b/src/hls/PrintHTL.ml @@ -87,15 +87,31 @@ let print_control pp f = fprintf pp " clk: %s\n" (register f.mod_clk); fprintf pp "}\n\n" +let print_scldecl pp (r, (io, sz)) = + fprintf pp " %s [%d:0]%s\n" (fst (print_io io)) (Nat.to_int sz - 1) (register (P.of_int r)) + +let print_arrdecl pp (r, (io, Verilog.VArray(sz, ln))) = + fprintf pp " %s [%d:0]%s[%d:0]\n" (fst (print_io io)) (Nat.to_int sz - 1) (register (P.of_int r)) (Nat.to_int ln - 1) + let print_module pp id f = fprintf pp "%s(%s) {\n" (extern_atom id) (registers f.mod_params); let externctrl = PTree.elements f.mod_externctrl in let datapath = ptree_to_list f.mod_datapath in let controllogic = ptree_to_list f.mod_controllogic in + let scldecls = ptree_to_list f.mod_scldecls in + let arrdecls = ptree_to_list f.mod_arrdecls in print_control pp f; + fprintf pp "scldecls {\n"; + List.iter (print_scldecl pp) scldecls; + fprintf pp " }\n\n"; + + fprintf pp "arrdecls {\n"; + List.iter (print_arrdecl pp) arrdecls; + fprintf pp " }\n\n"; + print_ram pp f.mod_ram; fprintf pp "externctrl {\n"; diff --git a/src/hls/PrintVerilog.mli b/src/hls/PrintVerilog.mli index dbb8ba0..6a996bd 100644 --- a/src/hls/PrintVerilog.mli +++ b/src/hls/PrintVerilog.mli @@ -25,3 +25,5 @@ val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit + +val print_io : Verilog.io option -> (string * bool) |