| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update and fix the transformation | Yann Herklotz | 2022-08-05 | 1 | -1/+1 |
| * | Rewrite a lot fixing scheduling of Gible | Yann Herklotz | 2022-05-27 | 1 | -10/+8 |
| * | Fix generation of RTLParFU | Yann Herklotz | 2021-11-17 | 1 | -0/+3 |
| * | Merge remote-tracking branch 'origin/dev/divider' into dev/scheduling | Yann Herklotz | 2021-11-16 | 1 | -4/+4 |
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| | * | Add RTLPar printing | Yann Herklotz | 2021-02-22 | 1 | -4/+7 |
| * | | Rename the verilator script | Yann Herklotz | 2021-11-13 | 1 | -35/+0 |
| * | | Add a Verilator driver | Yann Herklotz | 2021-11-11 | 1 | -0/+35 |
| * | | Fix compilation of new intermediate languages | Yann Herklotz | 2021-10-01 | 1 | -0/+3 |
| * | | Add back scheduling to the driver | Yann Herklotz | 2021-09-30 | 1 | -1/+1 |
| * | | Revert "Remove more OCaml files to compile successfully without admits." | Yann Herklotz | 2021-09-27 | 1 | -0/+1 |
| * | | Remove more OCaml files to compile successfully without admits. | Yann Herklotz | 2021-07-11 | 1 | -1/+0 |
| * | | Remove unnecessary files and proofs | Yann Herklotz | 2021-07-11 | 1 | -1/+1 |
| * | | Add option to turn on/off ram inferrence | Yann Herklotz | 2021-03-02 | 1 | -1/+3 |
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| * | Add option to turn off if-conversion | Yann Herklotz | 2021-02-16 | 1 | -1/+3 |
| * | Fix main buildv1.1.0 | Yann Herklotz | 2020-12-17 | 1 | -1/+1 |
| * | Add optimisations to output | Yann Herklotz | 2020-11-02 | 1 | -1/+4 |
| * | Add flag to control if scheduling is active | Yann Herklotz | 2020-11-01 | 1 | -2/+7 |
| * | Add printing of intermediate rtlblock language | Yann Herklotz | 2020-10-23 | 1 | -0/+4 |
| * | Finish implementing scheduling and add top level export | Yann Herklotz | 2020-10-20 | 1 | -1/+1 |
| * | Add scheduling to driver | Yann Herklotz | 2020-10-18 | 1 | -2/+2 |
| * | Fix compilation | Yann Herklotz | 2020-09-28 | 1 | -2/+2 |
| * | Add fixes to run scheduling on compilation | Yann Herklotz | 2020-09-03 | 1 | -2/+2 |
| * | More renames to get it to compile | Yann Herklotz | 2020-07-24 | 1 | -0/+0 |
| * | Change name to Vericert | Yann Herklotz | 2020-07-14 | 2 | -55/+55 |
| * | Add htl pretty printing | Yann Herklotz | 2020-06-30 | 1 | -0/+4 |
| * | Add command line flags for initial block | Yann Herklotz | 2020-06-30 | 1 | -5/+3 |
| * | Add print for debug always block in module | Yann Herklotz | 2020-06-22 | 1 | -1/+4 |
| * | Fix main function | Yann Herklotz | 2020-06-12 | 1 | -17/+3 |
| * | Improve the printing of results | Yann Herklotz | 2020-04-22 | 1 | -4/+5 |
| * | Update driver to support simulator | Yann Herklotz | 2020-04-17 | 1 | -15/+60 |
| * | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 1 | -2/+2 |
| * | Fix the Makefile build | Yann Herklotz | 2020-03-31 | 1 | -0/+0 |
| * | Remove main driver | Yann Herklotz | 2020-03-31 | 1 | -19/+0 |
| * | Add main file and global building | Yann Herklotz | 2020-03-31 | 2 | -6/+440 |
| * | Move compiler | Yann Herklotz | 2020-03-29 | 1 | -97/+0 |
| * | Move driver | Yann Herklotz | 2020-03-25 | 3 | -0/+125 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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