index
:
vericert
debug/unhashed
dev-michalis
dev/asplos
dev/div
dev/divider
dev/full-nix-build
dev/mac-op
dev/michalis
dev/scheduling
dev/value
exp/inl-cse-const
master
stable
Vericert is a formally verified high-level synthesis tool.
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path:
root
/
src
/
hls
/
HTLgenspec.v
Commit message (
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)
Author
Age
Files
Lines
*
Solve easier branches of the transf_instr proof
Michalis Pardalos
2021-05-06
1
-29
/
+64
*
Clean up iter_expand_instr_spec proof
Michalis Pardalos
2021-05-05
1
-21
/
+10
*
Solve iter_expand_instr_spec by tactic (not Icall)
Michalis Pardalos
2021-05-05
1
-105
/
+179
*
Add lemmas relating to new HTLgen operations
Michalis Pardalos
2021-05-03
1
-49
/
+71
*
Add some statements about externctrl to tr_code
Michalis Pardalos
2021-05-03
1
-9
/
+13
*
Give a (questionable) translation spec for HTLgen
Michalis Pardalos
2021-05-02
1
-12
/
+24
*
Simplify some HTLgenspec proofs
Michalis Pardalos
2021-05-02
1
-2
/
+2
*
Tie all modules' clock to main
Michalis Pardalos
2021-04-30
1
-4
/
+33
*
Get HTLgenproof to compile
Michalis Pardalos
2021-04-20
1
-86
/
+87
*
[WIP] HTLgenspec proof
Michalis Pardalos
2021-04-17
1
-46
/
+34
*
Add idle state after return
Michalis Pardalos
2021-03-01
1
-27
/
+30
*
Merge branch 'michalis' of https://github.com/mpardalos/vericert into michali...
Yann Herklotz
2021-02-16
1
-13
/
+49
*
Fix imports to remove warnings when compiling
Yann Herklotz
2021-01-22
1
-4
/
+14
*
Add correct copyright notices in files
Yann Herklotz
2021-01-10
1
-0
/
+1
*
Add RTLBlock intermediate language
Yann Herklotz
2020-08-30
1
-0
/
+641