Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Fix printing of the final cycle count | Yann Herklotz | 2021-02-21 | 1 | -2/+15 |
* | Add more legible names to variables | Yann Herklotz | 2021-02-12 | 1 | -1/+17 |
* | Fix state generation for if-conversion | Yann Herklotz | 2021-02-03 | 1 | -3/+9 |
* | Add predicated values and instructions | Yann Herklotz | 2021-02-02 | 1 | -0/+1 |
* | Add correct copyright notices in files | Yann Herklotz | 2021-01-10 | 1 | -0/+1 |
* | Fix pretty printing bug in Verilog | Yann Herklotz | 2020-11-02 | 1 | -2/+2 |
* | Fix printing of negative numbers | Yann Herklotz | 2020-10-23 | 1 | -1/+5 |
* | Add RTLBlock intermediate language | Yann Herklotz | 2020-08-30 | 1 | -0/+232 |