aboutsummaryrefslogtreecommitdiffstats
path: root/src/hls/Verilog.v
Commit message (Collapse)AuthorAgeFilesLines
* Clean up proofsYann Herklotz2022-10-111-28/+28
|
* Remove literal files againYann Herklotz2022-03-261-43/+76
|
* Fix up some more documentationYann Herklotz2022-02-251-56/+24
|
* Merge remote-tracking branch 'origin/dev/divider' into dev/schedulingYann Herklotz2021-11-161-19/+48
|\
| * Add beginning to scheduling divisionYann Herklotz2021-02-151-229/+71
| |
* | Fix warnings for Coq 8.13.2Yann Herklotz2021-10-091-9/+9
| |
* | Finish load and store proof, but broke top-levelYann Herklotz2021-04-061-0/+37
| |
* | Finish Veriloggenproof completelyYann Herklotz2021-04-041-16/+83
| |
* | Move implicit argsYann Herklotz2021-03-151-2/+2
| |
* | Fix Verilog importsYann Herklotz2021-03-141-14/+20
| |
* | Remove comments in Verilog.vYann Herklotz2021-03-141-194/+0
| |
* | Add negative edge reasoning to HTLgenproofYann Herklotz2021-03-091-0/+33
| |
* | Change lists in case statements to stmnt_listYann Herklotz2021-03-011-7/+22
|/
* Add Vrange and predicatesYann Herklotz2021-02-021-0/+2
|
* Add correct copyright notices in filesYann Herklotz2021-01-101-0/+1
|
* Update definition of VnegYann Herklotz2020-11-071-1/+1
|
* Add RTLBlock intermediate languageYann Herklotz2020-08-301-0/+893