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path: root/src/hls/Veriloggen.v
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* Annonimize submissiondev/asplosYann Herklotz2023-08-101-1/+1
* Add beginning to memory generation proofYann Herklotz2023-07-291-11/+30
* Place both case statements into the same always blockYann Herklotz2022-05-311-4/+5
* Fix compilation with new HTL languageYann Herklotz2021-11-181-26/+5
* Use new RAM defined in FunctionalUnits.vYann Herklotz2021-11-151-0/+1
* Finish Veriloggenproof completelyYann Herklotz2021-04-041-11/+10
* Add new enable interfaceYann Herklotz2021-04-011-2/+2
* Add memory disableYann Herklotz2021-03-311-2/+4
* Prove very top-level theoremYann Herklotz2021-03-191-3/+3
* Update RAM generation proofsYann Herklotz2021-03-091-6/+10
* Add RAM semantics to HTL and fix proofYann Herklotz2021-03-031-1/+1
* Add Verilog generation for ramsYann Herklotz2021-03-021-18/+47
* Change lists in case statements to stmnt_listYann Herklotz2021-03-011-2/+2
* Fix imports to remove warnings when compilingYann Herklotz2021-01-221-18/+23
* Add RTLBlock intermediate languageYann Herklotz2020-08-301-0/+65
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