Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Make externctrl application its own HTL pass | Michalis Pardalos | 2021-06-06 | 1 | -173/+25 |
* | Handle declarations of externctrl regs in Verilog | Michalis Pardalos | 2021-05-01 | 1 | -24/+41 |
* | Remove some dead code from Veriloggen | Michalis Pardalos | 2021-05-01 | 1 | -17/+0 |
* | Fix typo bug in applying externctrl | Michalis Pardalos | 2021-05-01 | 1 | -2/+2 |
* | Print externctrl in HTL debug output | Michalis Pardalos | 2021-05-01 | 1 | -5/+10 |
* | Apply externctrl mapping in HTL->Verilog stage | Michalis Pardalos | 2021-04-30 | 1 | -22/+147 |
* | Move renumbering to be HTL->HTL | Michalis Pardalos | 2021-04-20 | 1 | -230/+12 |
* | Typos in Veriloggen | Michalis Pardalos | 2021-03-01 | 1 | -2/+2 |
* | Unset finish signal on reset | Michalis Pardalos | 2021-02-28 | 1 | -1/+3 |
* | Merge branch 'michalis' of https://github.com/mpardalos/vericert into michali... | Yann Herklotz | 2021-02-16 | 1 | -44/+339 |
* | Fix imports to remove warnings when compiling | Yann Herklotz | 2021-01-22 | 1 | -18/+23 |
* | Add RTLBlock intermediate language | Yann Herklotz | 2020-08-30 | 1 | -0/+65 |