| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add proof to final_states | Yann Herklotz | 2020-06-02 | 1 | -2/+2 |
| * | Copy over RTL global state | Yann Herklotz | 2020-06-01 | 1 | -8/+15 |
| * | Fix compilation moving to PTree | Yann Herklotz | 2020-05-29 | 1 | -4/+3 |
| * | Fix the semantics to properly evaluate the state | Yann Herklotz | 2020-05-20 | 1 | -2/+4 |
| * | Add AssocMap | Yann Herklotz | 2020-05-08 | 1 | -5/+5 |
| * | Redefine HTL for intermediate Verilog language | Yann Herklotz | 2020-05-07 | 1 | -76/+69 |
| * | Add documentation and fix makefile for Compcert | Yann Herklotz | 2020-03-31 | 1 | -0/+25 |
| * | Remove unnecessary examples from HTL | Yann Herklotz | 2020-03-29 | 1 | -4/+4 |
| * | Update printing | Yann Herklotz | 2020-03-25 | 1 | -35/+41 |
| * | Rename to HTL | Yann Herklotz | 2020-03-23 | 1 | -0/+73 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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