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* Fix compilation moving to PTreeYann Herklotz2020-05-291-7/+7
* Switch position of empty ruleYann Herklotz2020-05-201-4/+4
* Add AssocMapYann Herklotz2020-05-081-39/+25
* Use associations instead of stateYann Herklotz2020-05-071-70/+65
* Rename assoclist to assocsetYann Herklotz2020-05-071-25/+25
* Minimised manual simulationYann Herklotz2020-05-051-10/+10
* Simplifications to proofYann Herklotz2020-05-051-2/+8
* Add equality check for valueYann Herklotz2020-05-041-1/+1
* Refine the semanticsYann Herklotz2020-05-041-42/+63
* Change to StateYann Herklotz2020-05-031-21/+22
* Add CompCert semantics for VerilogYann Herklotz2020-04-241-81/+152
* Add stmnt_runp inductiveYann Herklotz2020-04-221-27/+106
* Use State in semantics instead of splitting it upYann Herklotz2020-04-221-95/+98
* Fix Verilog.vYann Herklotz2020-04-171-1/+1
* Add main module runYann Herklotz2020-04-171-50/+78
* Add Verilog semantics with new Verilog moduleYann Herklotz2020-04-151-33/+326
* Handle loops and conditionals correctlyYann Herklotz2020-04-021-7/+8
* Update compilationYann Herklotz2020-04-011-5/+36
* Add documentation and fix makefile for CompcertYann Herklotz2020-03-311-1/+1
* Add more operators and print themYann Herklotz2020-03-311-3/+10
* Improve Verilog error messagesYann Herklotz2020-03-311-1/+4
* Change Verilog AST back to more traditional ASTYann Herklotz2020-03-291-30/+44
* Update AST and value representationsYann Herklotz2020-03-291-213/+42
* Rename Verilog AST filesYann Herklotz2020-03-291-0/+253
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