| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Change Verilog AST back to more traditional AST | Yann Herklotz | 2020-03-29 | 1 | -30/+44 |
| * | Remove unnecessary examples from HTL | Yann Herklotz | 2020-03-29 | 1 | -4/+4 |
| * | Update AST and value representations | Yann Herklotz | 2020-03-29 | 1 | -213/+42 |
| * | Rename Verilog AST files | Yann Herklotz | 2020-03-29 | 3 | -0/+0 |
| * | Update printing | Yann Herklotz | 2020-03-25 | 3 | -38/+52 |
| * | Remove dunes and make the build recursive | Yann Herklotz | 2020-03-25 | 1 | -4/+0 |
| * | Rename to HTL | Yann Herklotz | 2020-03-23 | 1 | -18/+28 |
| * | Create intermediate VTL language | Yann Herklotz | 2020-03-22 | 1 | -0/+63 |
| * | Add compcert library to coquplib | Yann Herklotz | 2020-03-22 | 1 | -8/+9 |
| * | Lower case folders | Yann Herklotz | 2020-03-19 | 4 | -0/+341 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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