Commit message (Expand) | Author | Age | Files | Lines | ||
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* | Add hex notation to values | Yann Herklotz | 2020-05-03 | 1 | -0/+9 | |
* | Change to State | Yann Herklotz | 2020-05-03 | 1 | -21/+22 | |
* | Add documentation and conform to specification | Yann Herklotz | 2020-04-29 | 1 | -24/+41 | |
* | Add CompCert semantics for Verilog | Yann Herklotz | 2020-04-24 | 1 | -81/+152 | |
* | Add valueToInt function | Yann Herklotz | 2020-04-24 | 1 | -0/+3 | |
* | Add stmnt_runp inductive | Yann Herklotz | 2020-04-22 | 1 | -27/+106 | |
* | Return the actual result of the module | Yann Herklotz | 2020-04-22 | 1 | -2/+5 | |
* | Remove unnecessary Lemma | Yann Herklotz | 2020-04-22 | 1 | -8/+1 | |
* | Use State in semantics instead of splitting it up | Yann Herklotz | 2020-04-22 | 1 | -95/+98 | |
* | Improve printing of results | Yann Herklotz | 2020-04-22 | 2 | -7/+13 | |
* | Fix Verilog.v | Yann Herklotz | 2020-04-17 | 1 | -1/+1 | |
* | Add main module run | Yann Herklotz | 2020-04-17 | 2 | -51/+79 | |
* | Fix printing with new Verilog AST | Yann Herklotz | 2020-04-17 | 2 | -26/+54 | |
* | Only generate clocked always blocks | Yann Herklotz | 2020-04-17 | 1 | -13/+13 | |
* | Extract simulator | Yann Herklotz | 2020-04-17 | 2 | -5/+5 | |
* | Add Simulator.v | Yann Herklotz | 2020-04-17 | 1 | -0/+32 | |
* | Add do notation for option | Yann Herklotz | 2020-04-15 | 1 | -0/+11 | |
* | Make proofs simpler using auto | Yann Herklotz | 2020-04-15 | 1 | -59/+45 | |
* | Add Verilog semantics with new Verilog module | Yann Herklotz | 2020-04-15 | 1 | -33/+326 | |
* | Create Value module for bitvectors | Yann Herklotz | 2020-04-15 | 1 | -0/+217 | |
* | Add proof about state wf | Yann Herklotz | 2020-04-08 | 1 | -40/+193 | |
* | Add partial proof of well formed state | Yann Herklotz | 2020-04-06 | 1 | -24/+136 | |
* | Fix extraction on linux | Yann Herklotz | 2020-04-02 | 1 | -1/+1 | |
* | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 3 | -112/+181 | |
* | Complete translation from simple RTL to Verilog | Yann Herklotz | 2020-04-01 | 1 | -101/+162 | |
* | Update compilation | Yann Herklotz | 2020-04-01 | 5 | -17/+84 | |
* | Convert from RTL to Verilog directly | Yann Herklotz | 2020-03-31 | 3 | -21/+45 | |
* | Add documentation and fix makefile for Compcert | Yann Herklotz | 2020-03-31 | 5 | -76/+101 | |
* | Add more operators and print them | Yann Herklotz | 2020-03-31 | 3 | -41/+84 | |
* | Use Compcert extraction | Yann Herklotz | 2020-03-31 | 1 | -2/+161 | |
* | Improve Verilog error messages | Yann Herklotz | 2020-03-31 | 2 | -2/+11 | |
* | Fix Verilog printing | Yann Herklotz | 2020-03-31 | 2 | -33/+35 | |
* | Add main file and global building | Yann Herklotz | 2020-03-31 | 1 | -6/+0 | |
* | Rename to transf_program | Yann Herklotz | 2020-03-29 | 1 | -1/+1 | |
* | Move compiler | Yann Herklotz | 2020-03-29 | 1 | -0/+113 | |
* | Complete conversion from HTL to Verilog | Yann Herklotz | 2020-03-29 | 1 | -8/+91 | |
* | Change Verilog AST back to more traditional AST | Yann Herklotz | 2020-03-29 | 1 | -30/+44 | |
* | Add Verilog generation from HTL | Yann Herklotz | 2020-03-29 | 1 | -0/+135 | |
* | Remove unnecessary examples from HTL | Yann Herklotz | 2020-03-29 | 2 | -10/+5 | |
* | Update AST and value representations | Yann Herklotz | 2020-03-29 | 1 | -213/+42 | |
* | Rename Verilog AST files | Yann Herklotz | 2020-03-29 | 3 | -0/+0 | |
* | Update printing | Yann Herklotz | 2020-03-25 | 4 | -38/+56 | |
* | Remove dunes and make the build recursive | Yann Herklotz | 2020-03-25 | 4 | -13/+5 | |
* | Create HTLgen | Yann Herklotz | 2020-03-25 | 3 | -148/+5 | |
* | Move driver | Yann Herklotz | 2020-03-25 | 3 | -126/+0 | |
* | Add Maps and HTL.v | Yann Herklotz | 2020-03-25 | 2 | -0/+235 | |
* | Rename to HTL | Yann Herklotz | 2020-03-23 | 1 | -18/+28 | |
* | Create intermediate VTL language | Yann Herklotz | 2020-03-22 | 1 | -0/+63 | |
* | Create a new direct translation | Yann Herklotz | 2020-03-22 | 2 | -14/+125 | |
* | Add compcert library to coquplib | Yann Herklotz | 2020-03-22 | 2 | -8/+13 |